1. Technical Field
The present invention is related to an electrostatic discharge (ESD) protection circuit, and more particularly to an ESD protection circuit designed for use in high frequency circuits.
2. Background Information
Electrostatic charge is typically created by the contact and separation of two materials: many persons have felt the electrical shock that can occur when one touches a conducting surface after having walked across a carpet. These discharges commonly range between 2000 and 4500 volts and are discharged over a few milliseconds; they appear to the victim as an attention-getting, but harmless, electrical shock: the human body provides a high resistance to the discharge of these significant voltages, thereby decreasing the associated current. (The human body model standard assumes that the human body has a capacitance of 100 picofarads (pf) and a series resistance of 1500 ohms. Thus, the peak current flow during a human body ESD event is generally on the order of amps.)
The buildup of electrostatic charge may also occur when charges accumulate upon an ungrounded surface or an electrically non-conductive surface. For example, a piece of equipment, an electronic circuit, or the like, which is not grounded, may collect charges as it is moved from one location to another. An electronic device sliding into or out of a bag can also generate an electrostatic charge. When the charged equipment touches an electrical conductor, an ESD event may occur. The electric current will follow the path of least resistance to the conductor. Unfortunately, the path of least resistance is often through vital electronic circuitry: In microelectronic systems, the conductor is often a prong of a packaged integrated circuit chip.
The wide-spread use of sensitive semiconductor chips in today's industrial and commercial products has made ESD protection a major concern in the design, layout, fabrication, and production of chips. Unlike the human body, which can easily dissipate an ESD event, semiconductor chips are extremely sensitive to ESD. Depending on the technology used in a chip, the maximum safe voltage the internal circuit elements can tolerate varies from approximately five volts to approximately twenty volts. As such, the mere touching of a chip by a non-grounded person or tool may result in an ESD event which can permanently damage the delicate electronic structures in an unprotected chip, possibly rendering the chip useless.
An ESD event through an integrated circuit (IC) can permanently damage the integrated circuit through several failing mechanisms, including the dielectric breakdown of oxides and other thin layers, the melting of conductive material such as polysilicon or aluminum, and the melting of semi-conductive material such as silicon, resulting in excessive leakage currents and open or short circuits in the IC.
To prevent ESD from damaging semiconductor circuits, various protective schemes may be employed. Large-scale protective schemes are often used to protect system level equipment. Examples of these schemes include, but are not limited to, the following: electrical grounding of technicians via wrist bands; the prevention of electrostatic build-up through the use of static-safe clothing, static control shoes, and high humidification; and the use of specialized shipping containers and storage bags. All of the above methods help to prevent the build-up of static charge. Additionally, small-scale, chip specific approaches may be used. Often, high-current clamping devices are placed on the pins of a chip so that the high currents associated with an ESD event are safely shunted away from the circuitry.
Ideally, such clamping devices are transparent during normal chip operations but shunt the high current of an ESD event away from the circuit being protected. This is typically accomplished by using an ESD protection device which is normally “off” but will turn on at a voltage that is well above a chip's normal operating voltage, but below a voltage that can damage the elements of an IC. When the ESD protection device is on, the excess current is passed through the ESD protection device instead of the current traveling through the circuit being protected.
While these circuits perform adequately in circuits that operate at low frequencies, they can adversely effect the operation of high frequency circuits.
The placement of an ESD protection circuit creates a large capacitance due to the ESD protection at the pad. The ESD parasitic capacitance becomes a significant problem around 1-2 GHz of operation; the reactance of the capacitance of a typical ESD protection circuit (1-2 pF) is almost as low as that of the transmission line: it can be very difficult to make a resistive termination with such a large capacitive load. Therefore, a part of the signal is lost through the ESD protection circuit. As a result, high frequency devices often do not include any ESD protection.
Because ESD protection is just as important for high-frequency circuits as it is for lower-frequency circuits, there is a need for an on-chip ESD protection circuit that operates without adversely affecting the performance of the high-frequency circuit.